Vice President, Pathfinding for System Integration, TSMC
Dr. Douglas Yu is a Distinguished Fellow and Vice President of Pathfinding for System Integration at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), responsible for forward looking study on advanced system integration technology.
Dr. Yu joined TSMC in 1994, serving in a variety of roles throughout his career including SoC backend processing technology R&D. In that role, he developed technologies critical to the Company’s highly successful transition to copper process at the 0.13 micron generation. Dr. Yu also pioneered TSMC’s 3DFabric™, aka WLSI (wafer-level system integration) technology platform and delivered Chip-on-Wafer-on-Substrate (CoWoS®), Integrated Fan-Out (InFO), and TSMC System-on-Integrated-Chips (SoIC™), as well as their derivatives. Prior to joining TSMC, Dr. Yu was a Member of Technical Staff and Project Leader at AT&T Bell Labs in USA, working on sub-micron process, low power device and integration technologies R&D.
Dr. Yu became an IEEE Fellow in 2013 and received the Presidential Science Prize (highest Taiwan science award 2017), IEEE EPS Outstanding Manufacturing Technology Award (2018), and IEEE Rao Tummala Award (EPS technical field award 2022). He has been granted > 1,400 US patents and published numerous journal and conference papers. He received his B.S. degree in Physics and M.S. degree in Materials Science and Engineering both from National Tsing Hua University, Taiwan and Ph.D. in Materials Engineering from Georgia Institute of Technology, USA.
Semiconductor technology migration has followed Moore’s Law in chip scaling for around 60 years. Along those years, advanced materials have been introduced to enable chip (system-on-chip, SoC) scaling and provide performance, power efficiency and area/size values. When it becomes more challenging to continue Moore’s Law, wafer-level-system integration technologies, such as 2.5D and 3DIC have emerged to achieve system-on-package (SoP) scaling to enable system-level performance, power efficiency and size/volume values. System integration of chiplets is complementary to SoC scaling and support Moore’s Law extension. Advanced materials are also introduced in the packaging to realize the SoP scaling.
The implementation of new and advanced materials often introduces various kind of processing and integration challenges to be addressed. In this presentation, we will review some examples of introducing advanced materials in both SoC and SoP on their challenges and the approaches to resolve those issues. Looking forward, we would like to continue supply chain collaboration, innovation and leverage existing resources and capabilities to introduce more advanced materials to continue SoC- and SoP-Scaling.